In the field of integrated circuit (IC) design, cloning is an optimization technique that takes an original ‘launch’ stage, for example comprising a flip-flop, for a critical timing path and duplicates it for use with a timing critical portion of the circuit. The original launch stage remains the start point for non-critical timing paths, whilst the ‘clone’ launch stage becomes the start point for the critical timing path. In this manner, timing critical paths may be separated from the non-timing critical paths, resulting in reduced fan-out and output load for the timing critical path launch stage in the cloned arrangement as compared with the original arrangement. The logic for the critical timing path may then be ‘optimised’, whilst the original sampling latch and the non-critical timing path remain unaffected.
The cloning of stages in this manner can provide significant improvements to the achievable operating frequency of an IC design; cloning even 1% of all launch stages within an IC design can result in frequency improvements of up to 20%. However, large scale cloning can also result in a significant increase in area of the IC design. As such, it is desirable to only clone stages within those timing critical paths that would most benefit from being cloned, and to avoid unnecessary cloning of stages that would provide little (if any) timing improvements.
Due to the enormous numbers of timing paths within modern IC designs, identifying those stages that would most benefit from being cloned is a very complicated and time consuming process. As such, manually identifying stages to be cloned is not a practical solution to optimise the cloning of such stages. Another problem with implementing cloning manually is that it requires changes to be made at the register transfer level (RTL). However, this is not always possible where parts of the IC design involve 3rd party design blocks, and such changes in the RTL of such 3rd party design blocks may require architectural licences, etc., which are often extremely expensive to obtain. Thus, the necessary RTL changes that would be required to implement cloning manually within such 3rd party design blocks are often not possible.
A problem with typical current automated techniques for implementing the cloning of stages is that typically they involve cloning the launch stages for all critical paths, together with all of the combinational logic within the critical paths for those stages. As such, there is no assessment of how beneficial such cloning is for individual critical paths, typically resulting in a significant amount of unnecessary cloning, and thus unnecessary increase in area.
U.S. Pat. No. 536,435 discloses an automated method of identifying candidate gates for cloning within timing critical paths, and individually implementing such cloning for each candidate gate by way of updating a respective netlist to include the cloning of the candidate gate, re-tiling and re-buffering the modified netlist circuit, and then recalculating slack values to assess whether the cloning of the candidate has improved the timing values. If timing values are not improved, the netlist is reverted back to before that particular cloning was implemented. This process is performed for each candidate gate within each timing critical path. Advantageously, unnecessary cloning of gates which would provide little if any improvement may be avoided. However, the large number of potential timing critical paths, and thus the large number of potentially cloned stages, within an IC design (e.g. ˜500,000 potentially cloned stages) means that the amount of time such synthesis would require to assess all possible candidate gates within all timing critical paths is not practically feasible.